1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to arrangements of arrays and power supply circuits for operating a large storage capacity semiconductor memory device stably and at a high speed. A particular object of the invention relates to arrangements of arrays and power supply circuits for operating a large storage capacity clock synchronous type Dynamic Random Access Memory stably and at a high speed, and more specifically, to arrangements of arrays and power supply circuits in a multi-bank clock synchronous type semiconductor memory device.
2. Description of the Background Art
In order to eliminate difference in operation speed between a microprocessor and a Dynamic Random Access Memory (DRAM) serving as a main memory for data transfer at a high speed for example, a clock synchronous type Dynamic Random Access Memory (SDRAM) which takes in an external signal and inputs/outputs data in synchronization with a clock signal such as a system clock is used.
FIG. 33 is a timing chart for use in illustration of the operation of a conventional SDRAM at the time of reading data. In the SDRAM, an operation mode is designated by a combination of the states of a plurality of external signals. The combination of the states of the plurality of external signals is referred to as "command". In FIG. 33, at a rising edge of a clock signal CLK in clock cycle #1, a row address strobe signal /RAS is set to an L level, and a column address strobe signal /CAS and a write enable signal /WE are maintained at an H level to provide an active command. Once the active command is provided, an address signal AD applied concurrently is used as a row address signal X to internally select a row, and the addressed row is driven into a selected state.
At a rising edge of clock signal CLK in clock cycle #3, row address strobe signal /RAS and write enable signal /WE are maintained at an H level, and column address strobe signal /CAS is set to an L level. The state is called "read command", and a data reading is specified. Once the read command is provided, address signal AD applied concurrently is used as a column address signal Y to internally select a column. In the SDRAM, valid data is output after the passage of a clock cycle or clock cycles called "CAS latency" from the application of the read command. In FIG. 33, the CAS latency is 2, and valid data Q0 is output at a rising edge of clock signal CLK in clock cycle #5.
Column address signals are generated in a prescribed sequence using column address signal Y as the head address, memory cells are sequentially selected and data is read out in synchronization with clock signal CLK. The number of pieces of data sequentially read out since one read command is provided is called "burst length".
In FIG. 33, data reading for a burst length of 4 is shown. Data of the burst length are read out, and then an output high impedance state is attained. In the memory cell array inside, however, the addressed row is maintained in a selected state.
Then, at a rising edge of clock signal CLK in clock cycle #9, row address strobe signal /RAS and write enable signal /WE are set to an L level, and column address strobe signal /CAS is set to an H level. The state is called "precharge command", and an array which has been selected is driven into a non-selected state. More specifically, the selected row is driven into a non-selected state, and the bit lines inside are all returned to a prescribed precharge voltage level.
FIG. 34 is a timing chart for use in illustration of the states of external signals at the time of writing data to the SDRAM. Similarly to the data reading as shown in FIG. 33, an active command is provided in clock cycle #1, and current address signal AD is used as row address signal X to select a row.
Then in clock cycle #3, row address strobe signal /RAS is set to an H level, and column address strobe signal /CAS and write enable signal /WE are set to an L level. The state is called "write command", and specifies a data writing. Address signal AD applied concurrently is used as column address signal Y to write data. At the time of writing data, write data D0 is applied simultaneously with the application of the write command, and external write data D1, D2 and D3 are sequentially taken inside at rising edges of clock signal CLK in clock cycles #4, #5 and #6, respectively. These pieces of write data D0 to D3 are written into selected memory cells in a prescribed sequence. Also at the time of writing data, column address signal Y is used as the head address to generate column address signals inside in a prescribed sequence to select memory cells are selected. Once the data writing completes, a precharge command is provided in clock cycle #9, and the array in a selected state is driven into a non-selected state.
As shown in FIGS. 33 and 34, an external signal is taken inside at a rising edge of clock signal CLK for determining its state, the timing of the external signal is determined relative to clock signal CLK, a timing margin for a skew in the external signal does not have to be taken into account, which makes earlier the internal operation start timing and permits high speed accessing. Data which is sampled at a rising edge of clock signal CLK can be input/output at the same frequency as that of clock signal CLK, which permits data transfer at a high speed.
FIG. 35 is a schematic diagram of an arrangement of array blocks and internal power supply circuits in a conventional SDRAM. In FIG. 35, the conventional SDRAM has memory array blocks MB#0 to MB#3 arranged in respective regions formed by dividing a rectangular semiconductor chip CH into four regions. Memory array blocks MB#0 to MB#3 each have a 16M-bit storage capacity, for example, and each include a row address decoder for selecting a row, a column address decoder for selecting a column and a sense amplifier for sensing and amplifying data in a selected memory cell.
In a central region CRa for the longer-side direction of semiconductor chip CH, there are provided a sense power supply circuit SVDC for supplying power supply voltage to the sense amplifiers, a peripheral power supply circuit PVDC for supplying power supply voltage to the peripheral circuitry, and an array boosting circuit WBC for generating a boosted voltage Vpp transmitted onto a selected word line (arranged corresponding to a row). Internal power supply circuits SVDC, PVDC and WBC are arranged in central region CRa, because an input/output circuit and a control circuit are provided in a central region CRb for the shorter-side direction of semiconductor chip CH. This is also because the lengths of supply lines for transmitting these internal power supply voltages to memory array blocks MB#0 to MB#3 should be equal.
Sense power supply circuit SVDC internally lowers externally supplied power supply voltage to a low voltage level, and the peripheral power supply circuit lowers externally supplied power supply voltage. The external power supply voltages are thus lowered inside for the following reasons. External logics or processors have not been reduced in size as much as DRAMs. In order to secure the breakdown voltage characteristics of components (MOS transistors) reduced in size in the DRAM, power supply voltage should be lowered depending upon the degree of down sizing (in order to secure the breakdown voltage of a gate insulating film in a MOS transistor). Meanwhile, if the power supply voltage is lowered for external processor or logics, the operation speed is lowered as well (because the MOS transistor is not reduced in size as much.) External power supply voltage such as system power supply voltage is lowered in the DRAM, in order to secure the breakdown voltage of the components and the operation characteristics of the external logics or processor.
Array boosting circuit WBC is used for the following reasons. Boosted voltage Vpp is transmitted onto a selected word line. In the SDRAM, similarly to a standard DRAM, a memory cell includes an access transistor of an n channel MOS transistor and a capacitor. Therefore, in order to prevent the threshold voltage loss across the access transistor and surely write data at a full power supply voltage level into the capacitor, boosted voltage Vpp higher than the power supply voltage is transmitted onto the selected word line.
FIG. 36 is a diagram of a configuration of the sense power supply circuit and peripheral power supply circuit shown in FIG. 35. In FIG. 36, sense power supply circuit SVDC and peripheral power supply circuit PVDC have a common structure, and therefore the power supply circuits are denoted by VDC.
Internal power supply circuit VDC includes a comparator CMP for comparing an internal power supply voltage Vin and a reference voltage Vref at a prescribed voltage level, and a drive transistor DR connected between an external power supply node EX and an internal power supply line to supply current to the internal power supply line from external power supply node EX based on the output signal of comparator CMP.
If internal power supply voltage Vin is higher than reference voltage Vref, the output signal of comparator CMP attains a high level, drive transistor DR is turned off, and the current supplying from external power supply node EX to the internal power supply line is stopped. Meanwhile, if internal power supply voltage Vin is lower than reference voltage Vref, the output signal of comparator CMP attains a low level, the conductance of drive transistor DR increases, and current is supplied from external power supply node EX to the internal power supply line to raise the voltage level of internal power supply voltage Vin. Therefore, internal power supply voltage Vin is maintained substantially at the voltage level of reference voltage Vref. By setting the voltage level of reference voltage Vref to an appropriate value, internal power supply voltage Vin at a desired voltage level is generated.
FIG. 37 is a diagram showing a configuration of array boosting circuit WBC shown in FIG. 35. In FIG. 37, array boosting circuit WBC includes a charge pump circuit WBCa for performing a charge pumping operation in response to a clock signal CLKp to generate boosted voltage Vpp. Charge pump circuit WBCa takes advantage of the charge pump operation of the capacitor.
Use of such power supply circuit VDC and boosting circuit WBC is encountered with the following problems.
As shown in FIG. 35, sense power supply circuit SVDC is provided in central region CRa between memory array blocks MB#0 to MB#3. If memory array blocks MB#0 to MB#3 form one bank, a memory cell selecting operation is performed in each of array blocks MB#0 to MB#3. If the memory cell selecting operation is performed at a time in memory array blocks MB#0 to MB#3, sense power supply circuit SVDC should supply current to the sense amplifiers included in memory array blocks MB#0 to MB#3. Drive transistor DR in sense power supply circuit SVDC therefore must have large driving capability, and its size (channel width) is set sufficiently large. Therefore, current is passed across drive transistor DR having a large size (channel width) during a sensing operation, DC current at the time of sensing operation (active DC current: an average of operation current at the time of sensing operation) cannot be reduced, which gives rise to increase in current consumption.
Sense power supply circuit SVDC provided in central region CRa is not provided at a position at a completely equal distance from memory array blocks MB#0 to MB#3. Therefore, the lengths of power supply lines from sense power supply circuit SVDC to memory array blocks MB#0 to MB#3 are different. If the lengths of the sense power supply lines are different, the impedances of the sense power supply lines are different, and therefore the amounts of reduction in the sense amplifier power supply voltage in the sense power supply lines are different. As a result, if the current supply capability of sense power supply circuit SVDC is determined in view of a power supply voltage drop in a power supply line with small impedance (a voltage drop caused by current flowing at the time of sensing operation), a large voltage drop is caused in a sense power supply line with larger impedance, which makes difficult accurate sensing operation. If the current driving capability of sense power supply circuit SVDC is determined in view of a voltage drop in a sense amplifier power supply line with large impedance, unnecessary current is supplied to a sense power supply line with small impedance, in other words, unnecessary current is consumed. Therefore, the imbalance of the impedances of the sense amplifier power supply lines reduces the margin for the sense amplifier power supply voltage, and stable operation cannot be secured.
If the size (channel width) of drive transistor DR in sensing power supply circuit SVDC is increased, large current is passed across drive transistor DR at the time of sensing operation, to compensate for a drop in internal power supply voltage (sense amplifier power supply voltage) Vin. In this case, the large current causes ringing in internal power supply voltage Vin, internal power supply voltage Vin fluctuates and it takes a long period of time for the voltage to reach a stable level, so that the sensing operation can not be stably performed (because data in a memory cell is maintained at the sense amplifier power supply voltage level). In this case, it takes a long period of time for data in a memory cell read out onto each bit line to be stabilized, in other words, high speed accessing can not be achieved.
This is also true to peripheral power supply circuit PVDC.
Array boosting circuit WBC generates boosted voltage Vpp transmitted onto a selected word line. In this case, the lengths of boosted voltage transmission lines for memory array blocks MB#0 to MB#3 are different, the voltage levels of boosted voltage Vpp transmitted onto a selected word line in memory array blocks MB#0 to MB#3 are different, so that accurate writing of memory cell data cannot be secured. If the driving capability of array boosting circuit WBC is sufficiently made large, the voltage level of boosted voltage Vpp could be raised more than necessary. In this case, the breakdown voltage characteristics of gate insulating films in MOS transistors which are reduced in size cannot be sufficiently secured. If the driving capability of array boosting circuit WBC is considerably reduced in order to prevent the voltage level of boosted voltage Vpp from being raised, in sequentially selecting word lines at a high speed, a next word line could be selected before the voltage level of boosted voltage Vpp fully returns to the original voltage level, word line driving voltage at a desired voltage level cannot be transmitted onto a selected word line, high speed reading operation cannot be performed, and sensing timing must be delayed (because the conductance of the access transistor cannot be sufficiently larger by boosted voltage Vpp and charge transfer to a corresponding bit line from the capacitor cannot be performed at a high speed).
Memory array blocks MB#0 to MB#3 in the SDRAM shown in FIG. 35 each include a column decoder, a row decoder and a sense amplifier circuit. In the SDRAM, an operation mode is designated in the form of command, and a memory cell addressed in response to an address signal applied at the time of the application of the command is accessed. If, therefore, a bank address signal is applied simultaneously with the command, memory array blocks MB#0 to MB#3 can be operated as a bank (only a memory array block addressed by a bank address is operated.) Hence, by operating each bank in an interleaved manner, data can be serially accessed by switching between the banks at the time of switching between pages.
In the bank arrangement, however, the banks are driven into a selected state and a non-selected state (an array active state and an array non-active state) independently from each other. Sense power supply circuit SVDC therefore must continually operate to supply current to the sense amplifiers when the banks are driven in the interleaved manner, and the same is true with the peripheral circuit as well as array boosting circuit WBC. The same problem as the previously described single bank arrangement is therefore encountered in the case of this bank arrangement. This is particularly serious if the memory capacity is increased, for example, to 128M bits or 1G bit, and the number of memory cells included in memory array blocks MB#0 to MB#3 increases, because difference between the line impedances becomes significant.
FIG. 38 is a diagram of another power supply circuit arrangement of a conventional SDRAM. In the SDRAM shown in FIG. 38, sense power supply circuits SVDCa and SVDCb are provided in the outer peripheral region of a central region CRb of a semiconductor chip CH for its shorter-side direction. Sense power supply circuit CVDCa supplies power supply voltage to sense amplifier circuits included in memory array blocks MB#0 and MB#1. Sense power supply circuit SVDCb supplies power supply voltage to sense amplifier circuits included in memory array blocks MB#2 and MB#3.
A peripheral power supply circuit PVDC which supplies power supply voltage to the peripheral circuits and an array boosting circuit WBC which generates boosted voltage Vpp transmitted onto a selected word line are arranged in a central region CRa of semiconductor chip CH for its longer-side direction, similarly to the arrangement shown in FIG. 35.
In the arrangement of the power supply circuits shown in FIG. 38, two sense power supply circuits SVDCa and SVDCb are provided in order to stably supply current at the time of sensing operation when the largest amount of current is consumed. Here, sense power supply circuits SVDCa and SVDCb consume current substantially half that of the one sense power supply circuit arrangement. The size (channel width) of drive transistors included in sense power supply circuits SVDCa and SVDCb can be reduced and the current supplying capability can be reduced, while bit line charging current can be supplied stably at the time of sensing operation.
If the storage capacity of memory array blocks MB#0 to MB#3 increases, the number of memory cells increases accordingly, which increases the number of columns of memory cells. The maximum number of memory cells connected to one row is determined by the word line capacitance, and the number of memory cells connected to one column is determined based on the capacitance ratio of bit line capacitance and memory cell capacitor. If the memory capacity increases, the numbers of rows and columns increase as well. Therefore, the number of sense amplifiers increases, which accordingly increases sense current (bit line charging current) to be supplied by sense power supply circuits SVDCa and SVDCb, which makes it difficult to stably supply sense amplifying power supply voltage without causing oscillation (ringing) for such a large storage capacity memory.
Peripheral power supply circuit SVDC and array boosting circuit WBC are each commonly provided to memory array blocks MB#0 to MB#3 similarly to the arrangement shown in FIG. 35, and therefore the same problem caused by the arrangement shown in FIG. 35 is encountered.
Japanese Patent Laying-Open No. 9-74171, for example, discloses an arrangement of reducing signal propagation delay by providing memory array blocks in the periphery of a control circuit, setting equal the lengths of signal lines from the control circuit to the memory array blocks, for the purpose of operating the device at a high speed without increasing signal propagation delay from the control circuit in a mass storage memory. The prior art, however, simply takes into account the relation between the arrangement of the control circuit and the memory array blocks, and does not suggest anything about how to divide the memory array blocks into banks in the bank arrangement and how to arrange power supply circuits in the single bank arrangement and multi-bank arrangement.